module LockSignal(reset, icode, ifun, finished, hold, clk, lock);
input reset;
input [3:0] icode;
input [3:0] ifun;
input finished;
input hold;
input clk;

output reg lock;

wire lock_out;

Register lck(.in(lock), .out(lock_out), .clk(clk));

always @(*) begin
	if(!reset) begin
		lock <= 0;
	end else if(finished && !hold && icode == 12) begin
		if(ifun == 0) begin
			lock <= 1;
		end else begin
			lock <= 0;
		end
	end else begin
		lock <= lock_out;
	end
end



endmodule